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・ Network of Ethiopian Women's Associations
・ Network of European Foundations for Innovative Cooperation
・ Network of European Regions Using Space Technologies
・ Network of European Worldshops
・ Network of Excellence for Functional Biomaterials
・ Network of Free Ulema – Libya
・ Network of Hispanic Communicators
・ Network of Indian Professionals
・ Network of InterCultural Exchange
・ Network of International Business Schools
・ Network of International Christian Schools
・ Network of National Institutions in the Americas
・ Network of practice
・ Network of Schools of Public Policy, Affairs, and Administration
・ Network of Spiritual Progressives
Network on a chip
・ Network on Religion and Justice
・ Network on Terminal Architecture
・ Network One
・ Network operating system
・ Network operations center
・ Network operator matrix
・ Network packet
・ Network partition
・ Network performance
・ Network planning and design
・ Network Policy Server
・ Network probability matrix
・ Network Processing Forum
・ Network processor


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Network on a chip : ウィキペディア英語版
Network on a chip

Network on chip or network on a chip (NoC or NOC) is a communication subsystem on an integrated circuit (commonly called a "chip"), typically between intellectual property (IP) cores in a system on a chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs.
==Parallelism and scalability==
The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, a NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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